scientific article; zbMATH DE number 1844658

zbMATH Open1001.68652MaRDI QIDQ4786136FDOQ4786136

Authors: Frank Wolz, Reiner Kolla 

Publication date: 12 December 2002

Full work available at URL: http://link.springer.de/link/service/series/0558/bibs/2147/21470336

Title of this publication is not available (Why is that?)

Recommendations

• Technology mapping and placement for delay-minimization in LUT-based FPGA design
• scientific article; zbMATH DE number 1844631
• Implementing and clustering modules with complex delays
• On nominal delay minimization in LUT-based FPGA technology mapping
• scientific article; zbMATH DE number 1941112

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Mathematical problems of computer architecture (68M07)

Cited In (2)

• Title not available (Why is that?)
• On nominal delay minimization in LUT-based FPGA technology mapping

This page was built for publication:

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4786136)