Combinatorial cell design for CMOS libraries

DOI10.1016/S0167-9260(99)00024-3zbMATH Open0938.68979OpenAlexW2083346339MaRDI QIDQ4955657FDOQ4955657

Authors:

Publication date: 4 June 2000

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0167-9260(99)00024-3

Recommendations

• Cell selection from technology libraries for minimizing power
• scientific article; zbMATH DE number 3959288
• An algebraic technique for generating optimal CMOS circuitry in linear time
• Transistor chaining in static CMOS functional cells of arbitrary planar topology

zbMATH Keywords

delay-matchsize-match

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (5)

• A theory for the derivation of combination C-mos circuit designs
• Transistor chaining in static CMOS functional cells of arbitrary planar topology
• On the geometrical optimization of CMOS Hall cells, rectangular and square
• Cell selection from technology libraries for minimizing power
• An evaluation of the equivalent inverter modeling approach

This page was built for publication: Combinatorial cell design for CMOS libraries

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4955657)