Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

DOI10.1109/TSP.2005.843704MaRDI QIDQ5355708zbMATH OpenOpenAlexFDO

Authors Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen

Publication date 20 September 2017

Published in IEEE Transactions on Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tsp.2005.843704

Mathematics Subject Classification ID

Numerical methods for discrete and fast Fourier transforms (65T50) Application of orthogonal and other special functions (94A11) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited in

(5)

• Simplified biorthogonal discrete wavelet transform for VLSI architecture design
• VLSI architectures for the discrete wavelet transform
• Investigation of lifting-based hardware architectures for discrete wavelet transform
• Real-time signal processing for high-density microelectrode array systems
• Low-power, low-complexity bit-serial VLSI architecture for 1D discrete wavelet transform

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