Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
DOI10.1109/TSP.2005.843704zbMATH Open1370.94052OpenAlexW2142076542MaRDI QIDQ5355708FDOQ5355708
Authors: Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen 
Publication date: 20 September 2017
Published in: IEEE Transactions on Signal Processing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tsp.2005.843704
Numerical methods for discrete and fast Fourier transforms (65T50) Application of orthogonal and other special functions (94A11) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)
Cited In (5)
- VLSI architectures for the discrete wavelet transform
- Simplified biorthogonal discrete wavelet transform for VLSI architecture design
- Real-time signal processing for high-density microelectrode array systems
- Investigation of lifting-based hardware architectures for discrete wavelet transform
- Low-power, low-complexity bit-serial VLSI architecture for 1D discrete wavelet transform
This page was built for publication: Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5355708)
