VLSI architectures for the discrete wavelet transform

DOI10.1109/82.386170MaRDI QIDQ4849385zbMATH OpenOpenAlexFDO

Authors Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin

Publication date 4 February 1996

Published in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/82.386170

zbMATH Keywords

linear systolic arraysdiscrete wavelet transformVLSI architecturesMallat's pyramid algorithmrecursive pyramid algorithm

Mathematics Subject Classification ID

Numerical methods for discrete and fast Fourier transforms (65T50) Numerical algorithms for specific classes of architectures (65Y10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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• An integrated systolic array design for video compression
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• High speed modular systolic array-based DTCWT with parallel processing architecture for 2d image transformation on FPGA
• Creation of codes based on wavelet transformation and its application in ADV612 chips

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