Automated Technology for Verification and Analysis

DOI10.1007/B102065zbMATH Open1108.68517OpenAlexW3139984071MaRDI QIDQ5394201FDOQ5394201

Authors: Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers 

Publication date: 25 October 2006

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/b102065

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Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (1)

• Modular synthesis of timed circuits using partial orders on LPNs

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