Automated Technology for Verification and Analysis

DOI10.1007/B102065MaRDI QIDQ5394201zbMATH OpenOpenAlexFDO

Authors Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers

Publication date 25 October 2006

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/b102065

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

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Cited in

(1)

• Modular synthesis of timed circuits using partial orders on LPNs

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