Formal Methods for Hardware Verification

DOI10.1007/11757283zbMATH Open1182.68113OpenAlexW2475557998MaRDI QIDQ5899154FDOQ5899154

Authors: G. Cabodi, Marco Murciano 

Publication date: 2 May 2007

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11757283

Recommendations

• A light-weight framework for hardware verification
• The use of \(B\) to specify, design and verify hardware
• scientific article; zbMATH DE number 1330907
• A methodology for hardware verification using compositional model checking
• A methodology for hardware verification based on logic simulation
• A BDD-based verification method for large synthesized circuits
• scientific article; zbMATH DE number 1304992
• Simulation-based hardware verification with a graph-based specification

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

Cited In (10)

• Formal verification using edge-valued binary decision diagrams
• A word-level graph manipulation package
• Efficient combinational verification using overlapping local BDDs and a hash table
• BDD-based symbolic model checking
• Decision diagrams for verification
• Bddl: A Type System for Binary Decision Diagrams
• Theorem Proving in Higher Order Logics
• Application of BDDs in Boolean matching techniques for formal logic combinational verification
• Title not available (Why is that?)
• Title not available (Why is that?)

This page was built for publication: Formal Methods for Hardware Verification

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5899154)