Formal Methods for Hardware Verification

DOI10.1007/11757283MaRDI QIDQ5899154zbMATH OpenOpenAlexFDO

Authors G. Cabodi, Marco Murciano

Publication date 2 May 2007

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/11757283

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

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Cited in

(10)

• Formal verification using edge-valued binary decision diagrams
• A word-level graph manipulation package
• Efficient combinational verification using overlapping local BDDs and a hash table
• BDD-based symbolic model checking
• Decision diagrams for verification
• Bddl: A Type System for Binary Decision Diagrams
• Theorem Proving in Higher Order Logics
• Application of BDDs in Boolean matching techniques for formal logic combinational verification
• scientific article; zbMATH DE number 1863167 (Why is no real title available?)
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