A BDD-based verification method for large synthesized circuits

DOI10.1016/S0167-9260(97)00018-7zbMATH Open0905.68075WikidataQ126297841 ScholiaQ126297841MaRDI QIDQ3840902FDOQ3840902

Authors: C. A. J. van Eijk 

Publication date: 13 August 1998

Published in: Integration (Search for Journal in Brave)

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zbMATH Keywords

structural similarityformal verificationbinary decision diagramslogic synthesisequivalence checking

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (7)

• Efficient combinational verification using overlapping local BDDs and a hash table
• Polynomial Formal Verification of Approximate Functions
• Formal Methods for Hardware Verification
• A Mechanically Verified AIG-to-BDD Conversion Algorithm
• Application of BDDs in Boolean matching techniques for formal logic combinational verification
• Title not available (Why is that?)
• Title not available (Why is that?)

Uses Software

• HANNIBAL

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