A BDD-based verification method for large synthesized circuits

DOI10.1016/S0167-9260(97)00018-7MaRDI QIDQ3840902zbMATH OpenWikidataFDO

Authors C. A. J. van Eijk

Publication date 13 August 1998

Published in Integration (Search for Journal in Brave)

zbMATH Keywords

structural similarityformal verificationbinary decision diagramslogic synthesisequivalence checking

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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• Efficient combinational verification using overlapping local BDDs and a hash table
• Polynomial Formal Verification of Approximate Functions
• Formal Methods for Hardware Verification
• A Mechanically Verified AIG-to-BDD Conversion Algorithm
• Application of BDDs in Boolean matching techniques for formal logic combinational verification
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