Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays
DOI10.1007/S11241-018-9312-0zbMATH Open1436.68069OpenAlexW2809390521MaRDI QIDQ777069FDOQ777069
Authors: Borislav Nikolić, Sebastian Tobuschat, Leandro Soares Indrusiak, Rolf Ernst, Alan Burns 
Publication date: 13 July 2020
Published in: Real-Time Systems (Search for Journal in Brave)
Full work available at URL: https://eprints.whiterose.ac.uk/131704/1/authorversionRTSJNikolicetal.pdf
Recommendations
- Using non-preemptive regions and path modification to improve schedulability of real-time traffic over priority-based NOCs
- Schedulability analysis and task mapping for real-time on-chip communication
- Worst-case execution time analysis for many-core architectures with NoC
- Buffer planning for application-specific networks-on-chip design
- An analytical model for Network-on-Chip with finite input buffer
embedded systemsreal-time systemsnetwork-on-chipwormhole switchingpriority-preemptive arbitrationvirtual channels
Cites Work
- Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
- Schedulability analysis and task mapping for real-time on-chip communication
- Worst-case end-to-end delays evaluation for \texttt{SpaceWire} networks
- SLA: A Stage-Level Latency Analysisfor Real-Time Communicationin a Pipelined Resource Model
- Extending Real-Time Analysis for Wormhole NoCs
- dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up
Cited In (6)
- Modeling Cache Coherence to Expose
- Using non-preemptive regions and path modification to improve schedulability of real-time traffic over priority-based NOCs
- Schedulability analysis and task mapping for real-time on-chip communication
- Worst-case execution time analysis for many-core architectures with NoC
- nDimNoC: Real-Time D-dimensional NoC
- Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture
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