Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays
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Publication:777069
Recommendations
- Using non-preemptive regions and path modification to improve schedulability of real-time traffic over priority-based NOCs
- Schedulability analysis and task mapping for real-time on-chip communication
- Worst-case execution time analysis for many-core architectures with NoC
- Buffer planning for application-specific networks-on-chip design
- An analytical model for Network-on-Chip with finite input buffer
Cites work
- Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
- Extending Real-Time Analysis for Wormhole NoCs
- SLA: A Stage-Level Latency Analysisfor Real-Time Communicationin a Pipelined Resource Model
- Schedulability analysis and task mapping for real-time on-chip communication
- Worst-case end-to-end delays evaluation for \texttt{SpaceWire} networks
- dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up
Cited in
(6)- Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture
- Modeling Cache Coherence to Expose
- Schedulability analysis and task mapping for real-time on-chip communication
- Worst-case execution time analysis for many-core architectures with NoC
- nDimNoC: Real-Time D-dimensional NoC
- Using non-preemptive regions and path modification to improve schedulability of real-time traffic over priority-based NOCs
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