A single layer zero skew clock routing in X architecture

DOI10.1007/S11432-009-0028-6zbMATH Open1191.68132OpenAlexW2080367881MaRDI QIDQ848302FDOQ848302

Authors: Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, B. Lu 

Publication date: 3 March 2010

Published in: Science in China. Series F (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11432-009-0028-6

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zbMATH Keywords

clock routingsingle layerX architecturezero skew

Mathematics Subject Classification ID

Applications of graph theory (05C90) Graph algorithms (graph-theoretic aspects) (05C85) Planar graphs; geometric and topological aspects of graph theory (05C10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

Cites Work

• Zero skew clock routing with minimum wirelength
• Reliable buffered clock tree routing algorithm with process variation tolerance

Cited In (4)

• Legitimate skew clock routing with buffer insertion
• Reliable buffered clock tree routing algorithm with process variation tolerance
• Title not available (Why is that?)
• Minimizing Wirelength in Zero and Bounded Skew Clock Trees

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