A single layer zero skew clock routing in X architecture

DOI10.1007/s11432-009-0028-6zbMath1191.68132MaRDI QIDQ848302

Bing Lu, Xianlong Hong, Weixiang Shen, Yici Cai, Jiang Hu

Publication date: 3 March 2010

Published in: Science in China. Series F (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11432-009-0028-6

zbMATH Keywords

clock routing; single layer; X architecture; zero skew

Mathematics Subject Classification ID

05C90: Applications of graph theory

05C10: Planar graphs; geometric and topological aspects of graph theory

68W35: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.)

05C85: Graph algorithms (graph-theoretic aspects)

68M99: Computer system organization

Cites Work

• Reliable buffered clock tree routing algorithm with process variation tolerance
• Zero skew clock routing with minimum wirelength