Reliable buffered clock tree routing algorithm with process variation tolerance

MaRDI QIDQ866187zbMATH OpenFDO

Authors Yici Cai, Yan Xiong, Xianlong Hong, Yi Liu

Publication date 20 February 2007

Published in Science in China. Series F (Search for Journal in Brave)

Mathematics Subject Classification ID

Management decision making, including multiple objectives (90B50) Nonnumerical algorithms (68W05) Network design and communication in computer systems (68M10)

Recommendations

• Legitimate skew clock routing with buffer insertion
• Minimizing Wirelength in Zero and Bounded Skew Clock Trees
• A single layer zero skew clock routing in X architecture
• scientific article; zbMATH DE number 1305406
• Practical approximation algorithms for zero- and bounded-skew trees

Cited in

(3)

• Legitimate skew clock routing with buffer insertion
• A single layer zero skew clock routing in X architecture
• Variation-aware clock network buffer sizing using robust multi-objective optimization

This page was built for publication: Reliable buffered clock tree routing algorithm with process variation tolerance

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q866187)