The following pages link to Trace theory and VLSI design (Q1821550):
Displayed 14 items.
- Receptive process theory (Q758200) (← links)
- A formal approach to designing delay-insensitive circuits (Q808286) (← links)
- Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench (Q1029101) (← links)
- An alternative implementation of communication primitives (Q1091123) (← links)
- Compiling communicating processes into delay-insensitive VLSI circuits (Q1102258) (← links)
- On the existence of delay-insensitive fair arbiters: Trace theory and its limitations (Q1102260) (← links)
- Deadlock and fairness in morphisms of transition systems (Q1105379) (← links)
- Correctness of concurrent processes (Q1176236) (← links)
- Delay-insensitivity and ternary simulation (Q1575731) (← links)
- Locked discrete event systems: How to model and how to unlock (Q1802243) (← links)
- Progress assumption in concurrent systems (Q1805398) (← links)
- Infinite unfair shuffles and associativity (Q2373763) (← links)
- Synchronized shuffles (Q2566012) (← links)
- Computing and the cultures of proving (Q5301848) (← links)