The following pages link to Integration (Q2734603):
Displaying 50 items.
- A fast hypergraph min-cut algorithm for circuit partitioning (Q2734604) (← links)
- Redundant arithmetic, algorithms and implementations (Q2734606) (← links)
- Computation of capacitance matrix for integrated circuit interconnects using semi-analytic Green's function method (Q2734607) (← links)
- Test-set partitioning for multi-weighted random LFSRs (Q2734608) (← links)
- An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitions (Q2734609) (← links)
- Management of charge pump circuits (Q2734614) (← links)
- Delay-insensitive gate-level pipelining (Q2778429) (← links)
- Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate (Q2778430) (← links)
- Network flow based buffer planning (Q2778432) (← links)
- Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links (Q2778433) (← links)
- A bit-interleaved systolic architecture for a high-speed RSA system (Q2778434) (← links)
- Recent directions in netlist partitioning: a survey (Q3122465) (← links)
- Systolic algorithms for solving a sparse system of linear equations in circuit simulation (Q3122468) (← links)
- Performance optimization of VLSI interconnect layout (Q3122470) (← links)
- Built-in self-test for folded bit-line Mbit DRAMs (Q3122472) (← links)
- Synthesis of systems specified as interacting VHDL processes (Q3122474) (← links)
- The Retiming Lemma: A simple proof and applications (Q3122481) (← links)
- Resource-constrained scheduling of partitioned algorithms on processor arrays (Q3122482) (← links)
- A discrete formalization of switch-level circuit behavior (Q3122484) (← links)
- An efficient lower bound algorithm for channel routing (Q3122485) (← links)
- A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation (Q3122486) (← links)
- Testing asynchronous circuits: A survey (Q3122506) (← links)
- A new approach to the multiport memory allocation problem in data path synthesis (Q3122507) (← links)
- Minimum crosstalk switchbox routing (Q3122508) (← links)
- Diagnosis of interconnects using a structured walking-1 approach (Q3122509) (← links)
- Delay fault diagnosis in sequential circuits based on path tracing (Q3122510) (← links)
- Factored spherical subspace tracking (Q3122539) (← links)
- An algorithm and architecture based on orthonormal μ-rotations for computing the symmetric EVD (Q3122540) (← links)
- Scalable parallel processor array for Jacobi-type matrix computations (Q3122542) (← links)
- Communication code generation in systems of affine recurrence equations (Q3122543) (← links)
- The design of parallel square-root covariance Kalman filters using algorithm engineering (Q3122544) (← links)
- A dual basis bit-serial systolic multiplier for GF(2 ) (Q3122545) (← links)
- Architectures for large-capacity CAMs (Q3122547) (← links)
- Reliability and wirability optimizations for module placement on a convectively cooled printed wiring board (Q3122551) (← links)
- Fault tolerant arithmetic unit using duplication and residue codes (Q3122553) (← links)
- On the testability of iterative logic arrays (Q3122556) (← links)
- Pipelined recursive filter architectures for subband image coding (Q3136226) (← links)
- Systematic serialisation of array-based architectures (Q3136228) (← links)
- Partitioning of processor arrays: a piecewise regular approach (Q3136229) (← links)
- An improved systolic algorithm for the algebraic path problem (Q3136230) (← links)
- Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays (Q3136231) (← links)
- Orthogonal lattice algorithms for adaptive filtering and beamforming (Q3136233) (← links)
- Path-delay-fault testability properties of multiplexor-based networks (Q3139910) (← links)
- A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization (Q3139911) (← links)
- A unified approach for scheduling and allocation (Q3840893) (← links)
- Scheduling with multiple voltages (Q3840895) (← links)
- How good are slicing floorplans? (Q3840896) (← links)
- A complete testing strategy based on interacting and hierarchical FSMs (Q3840897) (← links)
- An embedded CDMA-receiver A design example (Q3840899) (← links)
- Mirroring: a technique for pipelining semi-systolic and systolic arrays (Q3840900) (← links)
