The following pages link to Xianlong Hong (Q848301):
Displaying 17 items.
- A single layer zero skew clock routing in X architecture (Q848302) (← links)
- Corner block list representation and its application with boundary constraints (Q866048) (← links)
- Reliable buffered clock tree routing algorithm with process variation tolerance (Q866187) (← links)
- (Q1412145) (redirect page) (← links)
- SSTT: Efficient local search for GSI global routing (Q1412147) (← links)
- FaSa: A fast and stable quadratic placement algorithm (Q1415932) (← links)
- An optimum placement search algorithm based on extended corner block list. (Q1433950) (← links)
- CNB: a critical-network-based timing optimization method for standard cell global routing (Q1884304) (← links)
- Determinstic VLSI block placement algorithm using less flexibility first principle (Q1884306) (← links)
- Legitimate skew clock routing with buffer insertion (Q2432131) (← links)
- Application of optical proximity correction technology (Q2481784) (← links)
- Preconditioned multi-zone boundary element analysis for fast 3D electric simulation (Q2486427) (← links)
- (Q4466821) (← links)
- Floorplanning with abutment constraints based on corner block list (Q4539953) (← links)
- Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization (Q4590521) (← links)
- (Q4790484) (← links)
- (Q4825733) (← links)
