Synthesis of delay fault testability circuits

DOI10.1109/12.536242MaRDI QIDQ4420874zbMATH OpenOpenAlexFDO

Authors Sreejit Chakravarty

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.536242

zbMATH Keywords

logic optimizationtestability enhancing transformations

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

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Cited in

(5)

• scientific article; zbMATH DE number 996555 (Why is no real title available?)
• Testing cross-talk induced delay faults in digital circuit based on transient current analysis
• Optimal design of hazard-free and easily testable logic networks
• Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method
• Gate-delay-fault testability properties of multiplexor-based networks

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