Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

DOI10.1109/TC.1986.1676825MaRDI QIDQ3716977zbMATH OpenOpenAlexFDO

Authors Sudhakar M. Reddy, Madhukar K. Reddy

Publication date 1986

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1986.1676825

zbMATH Keywords

test invalidationtestable designs

Mathematics Subject Classification ID

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• Nonstuck behaviour of open circuit supply faults in CMOS logic circuits
• Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring

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