True concurrency in models of asynchronous circuit behavior

DOI10.1023/A:1022902408130MaRDI QIDQ1870206zbMATH OpenOpenAlexFDO

Authors S. J. Silver, Janusz Brzozowski

Publication date 11 May 2003

Published in Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1022902408130

zbMATH Keywords

asynchronouscircuitdelay-insensitiveinterleavingmultiple-winnersemi-modularsingle-winnertrue concurrency

Mathematics Subject Classification ID

Computer system organization (68M99) Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10)

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(4)

• Weakly regular quantum grammars and asynchronous quantum automata
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• Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits
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