Vector sets for exhaustive testing of logic circuits
From MaRDI portal
Recommendations
Cited in
(44)- Covering arrays of strength 3 and 4 from holey difference matrices
- DNF are teachable in the average case
- Covering arrays avoiding forbidden edges
- An adaptive heuristic algorithm for VLSI test vectors selection
- Upper bounds for covering arrays by tabu search.
- Asymptotic and constructive methods for covering perfect hash families and covering arrays
- On the capacity of Boolean graph formulæ
- On the extremal combinatorics of the Hamming space
- An efficient design and implementation of the in-parameter-order algorithm
- Mixed optimization combinatorial method for constructing covering arrays
- Deterministic constructions of high-dimensional sets with small dispersion
- Sliced AETG: a memory-efficient variant of the AETG covering array generation algorithm
- The complexity of exact learning of acyclic conditional preference networks from swap examples
- A survey on the problems and algorithms for covering arrays via set covers
- The cell probe complexity of succinct data structures
- The test suite generation problem: optimal instances and their implications
- Mixed covering arrays on 3-uniform hypergraphs
- Locating and detecting arrays for interaction faults
- Covering arrays on graphs
- Exact learning from an honest teacher that answers membership queries
- Design of universal test sequences for VLSI
- On the Complexity of Estimating the Size of a Test Set
- Universal test sets for reversible circuits (extended abstract)
- Universal sets and the vector game
- scientific article; zbMATH DE number 3972795 (Why is no real title available?)
- scientific article; zbMATH DE number 4010401 (Why is no real title available?)
- Algebraic modelling of covering arrays
- Mixed covering arrays on graphs of small treewidth
- A hyperedge coloring and application in combinatorial testing
- \(t\)-CIS codes over \(\mathrm{GF}(p)\) and orthogonal arrays
- Subspace restrictions and affine composition for covering perfect hash families
- Upper bounds on the size of covering arrays
- Learning a circuit by injecting values
- The \(k\)-distinct language: parameterized automata constructions
- Finding a hidden code by asking questions
- A formal logic approach to constrained combinatorial testing
- Covering array on the Cartesian product of hypergraphs
- On one-sided testing affine subspaces
- Fooling near-maximal decision trees
- A survey of methods for constructing covering arrays
- Constraint models for the covering test problem
- Underapproximation for model-checking based on universal circuits
- Constructions of new orthogonal arrays and covering arrays of strength three
- Vertex Turán problems in the hypercube
This page was built for publication: Vector sets for exhaustive testing of logic circuits
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3799961)