A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
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Publication:4420928
DOI10.1109/12.485568zbMath1057.68754OpenAlexW2154098113MaRDI QIDQ4420928
Simon S. Liu, Vojin G. Oklobdzija, David Villeger
Publication date: 2 November 2003
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/12.485568
Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)
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