A Deductive Method for Simulating Faults in Logic Circuits

DOI10.1109/T-C.1972.223542MaRDI QIDQ5643892zbMATH OpenFDO

Authors Douglas B. Armstrong

Publication date 1972

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/T-C.1972.223542

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cited in

(6)

• Efficient VLSI fault simulation
• Confidence intervals for expected coverage from a beta testability model
• Electronic circuit diagnostic expert systems - a survey
• Evaluation of a fan out stem based fault simulation in sequential circuits
• A series of impulse functions as a model for random detectability profiles
• Parallel fault simulation on a multiprocessor

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