Automatic identification of spatial defect patterns for semiconductor manufacturing
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Recommendations
- Spatial defect pattern recognition on semiconductor wafers using model-based clustering and Bayesian inference
- Monitoring Wafer Map Data from Integrated Circuit Fabrication Processes for Spatially Clustered Defects
- A self-growing hidden Markov tree for wafer map inspection
- Development of a framework for analyzing process monitoring data with applications to semiconductor manufacturing process
- Model-based clustering for integrated circuit yield enhancement
Cites work
- Detecting Spatial Effects from Factorial Experiments: An Application from Integrated-Circuit Manufacturing
- scientific article; zbMATH DE number 3793445 (Why is no real title available?)
- Monitoring Wafer Map Data from Integrated Circuit Fabrication Processes for Spatially Clustered Defects
- On clustering validation techniques
- Regularized Gaussian Discriminant Analysis Through Eigenvalue Decomposition
- Wafer bin map recognition using a neural network approach
Cited in
(4)- Spatial defect pattern recognition on semiconductor wafers using model-based clustering and Bayesian inference
- A self-growing hidden Markov tree for wafer map inspection
- Monitoring Wafer Map Data from Integrated Circuit Fabrication Processes for Spatially Clustered Defects
- Wafer bin map recognition using a neural network approach
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