Design of bit parallel multiplier with lower time complexity

DOI10.1007/978-3-540-24691-6_11MaRDI QIDQ5714120zbMATH OpenOpenAlexFDO

Authors Seon Ok Lee, Seokwon Jung, Chang Han Kim, Jae-Young Koh, Dae Ho Kim, Janghong Yoon

Publication date 27 December 2005

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/b96249

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Analysis of algorithms and problem complexity (68Q25) Cryptography (94A60)

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(10)

• Efficient multiplier based on hybrid approach for Toeplitz matrix-vector product
• Parallel \(\mathrm{GF}(3^m)\) multiplier for trinomials
• Speedup of bit-parallel Karatsuba multiplier in \(\mathrm{GF}(m^2)\) generated by trinomials
• A survey of some recent bit-parallel \(\mathrm{GF}(2^n)\) multipliers
• Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers
• Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
• Improved Design of High-Performance Parallel Decimal Multipliers
• Efficient bit-parallel multipliers over finite fields GF(2ᵐ)
• Reduction-free multiplication for finite fields and polynomial rings
• Low complexity bit parallel multiplier for GF(2ᵐ) generated by equally-spaced trinomials

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