Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
From MaRDI portal
Recommendations
- Two's complement computation sharing multiplier and its applications to high performance DFE
- scientific article; zbMATH DE number 5708383
- Fast one's-complement multiplication
- Area—Time optimal VLSI integer multiplier with minimum computation time
- scientific article; zbMATH DE number 3887073
- Information Security and Cryptology - ICISC 2003
- Fast binary multiplication by performing dot counting and complement recoding
- Inefficiency of common-multiplicand multiplication and exponentiation algorithms by performing binary complements
- Area-Efficient Multipliers Based on Multiple-Radix Representations
- Efficient realization of large size two's complement multipliers using embedded blocks in FPGAs
Cited in
(4)
This page was built for publication: Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5280620)