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scientific article; zbMATH DE number 4018390
| Language | Label | Description | Also known as |
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| default for all languages | No label defined |
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| English | No label defined |
scientific article; zbMATH DE number 4018390 |
Statements
1986
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VLSI hierarchical verification
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proof of correctness
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behavioral description
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structural description
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synchrony
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asynchrony
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VLSI digital systems design
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dot calculus
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term-rewriting system
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wire
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comparator circuit
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0.7602376937866211
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0.7560781240463257
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0.7533974051475525
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