Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders

DOI10.1109/TCSI.2010.2055250MaRDI QIDQ5010540zbMATH OpenFDO

Authors Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TCSI.2010.2055250

Mathematics Subject Classification ID

Linear codes (general theory) (94B05) Decoding (94B35)

Cited in

(2)

• Energy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm
• High-throughput architectures for circular block-type low-density parity-check codes

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