Partially reconfigurable cores for Xilinx Virtex

DOI10.1007/3-540-46117-5_31MaRDI QIDQ4407343zbMATH OpenFDO

Authors M. Dyer, Christian Plessl, Marco Platzner

Publication date 29 June 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2438/24380292.htm

Mathematics Subject Classification ID

Computing methodologies and applications (68U99)

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Cited in

(8)

• Requirements for interfacing IP-components in re-configurable platforms
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• Using PARBIT to implement partial run-time reconfigurable systems
• A reconfigurable processor architecture
• Dynamically reconfigurable cores
• Reconfigurable breakpoints for co-debug
• Rapid construction of partial configuration datastreams for high-level constructs using JBits
• Optimization of a logic circuit implementing a Moore automaton in CPLD basis

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