| Publication | Date of Publication | Type |
|---|
| Certified knowledge compilation with application to verified model counting | 2024-11-26 | Paper |
| Clausal proofs for pseudo-Boolean reasoning | 2024-01-23 | Paper |
| Moving definition variables in quantified Boolean formulas | 2024-01-23 | Paper |
| Generating Extended Resolution Proofs with a BDD-Based SAT Solver | 2023-11-03 | Paper |
| Preprocessing of propagation redundant clauses | 2023-10-24 | Paper |
| Preprocessing of propagation redundant clauses | 2022-12-07 | Paper |
| Dual proof generation for quantified Boolean formulas with a BDD-based solver | 2021-12-01 | Paper |
| Generating extended resolution proofs with a BDD-based SAT solver | 2021-08-04 | Paper |
| Chain reduction for binary and zero-suppressed decision diagrams | 2020-11-02 | Paper |
| Chain reduction for binary and zero-suppressed decision diagrams | 2019-09-16 | Paper |
| On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication | 2018-09-14 | Paper |
| Binary Decision Diagrams | 2018-07-20 | Paper |
| Predicate abstraction with indexed predicates | 2017-07-12 | Paper |
| Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic | 2017-06-13 | Paper |
| Boolean satisfiability with transitivity constraints | 2017-06-13 | Paper |
| A symbolic approach to predicate abstraction. | 2010-04-20 | Paper |
| Deductive verification of advanced out-of-order microprocessors. | 2010-04-20 | Paper |
| Unbounded, fully symbolic model checking of timed automata using Boolean methods. | 2010-04-20 | Paper |
| Convergence testing in term-level bounded model checking | 2010-02-05 | Paper |
| FST TCS 2003: Foundations of Software Technology and Theoretical Computer Science | 2009-08-06 | Paper |
| State-set branching: leveraging BDDs for heuristic search | 2009-07-17 | Paper |
| Verification, Model Checking, and Abstract Interpretation | 2009-05-15 | Paper |
| Formal Verification of Infinite State Systems Using Boolean Methods | 2008-09-25 | Paper |
| A View from the Engine Room: Computational Support for Symbolic Model Checking | 2008-07-15 | Paper |
| Deciding Quantifier-Free Presburger Formulas Using Parameterized Solution Bounds | 2007-10-11 | Paper |
| On solving Boolean combinations of UTVPI constraints. | 2007-10-09 | Paper |
| Tools and Algorithms for the Construction and Analysis of Systems | 2007-09-28 | Paper |
| Deciding Bit-Vector Arithmetic with Abstraction | 2007-09-03 | Paper |
| On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication | 2007-01-09 | Paper |
| Automated Deduction – CADE-20 | 2006-11-01 | Paper |
| Computer Aided Verification | 2005-08-25 | Paper |
| Computer Aided Verification | 2005-08-25 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4818814 | 2004-09-24 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4818801 | 2004-09-24 | Paper |
| Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. | 2004-03-14 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4427901 | 2003-09-14 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4804898 | 2003-05-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4804887 | 2003-05-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4553255 | 2002-11-04 | Paper |
| Verification of arithmetic circuits using binary moment diagrams | 2002-07-25 | Paper |
| https://portal.mardi4nfdi.de/entity/Q2754075 | 2001-11-11 | Paper |
| Geometric characterization of series-parallel variable resistor networks | 1997-05-28 | Paper |
| A methodology for hardware verification based on logic simulation | 1995-03-30 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4037372 | 1993-05-18 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4037095 | 1993-05-18 | Paper |
| Graph-Based Algorithms for Boolean Function Manipulation | 1986-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4721964 | 1986-01-01 | Paper |
| A Switch-Level Model and Simulator for MOS Digital Systems | 1984-01-01 | Paper |
