Program compression on the instruction systolic array

DOI10.1016/S0167-8191(05)80106-1MaRDI QIDQ1175202zbMATH OpenOpenAlexFDO

Authors S. Singh

Publication date 25 June 1992

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0167-8191(05)80106-1

zbMATH Keywords

instruction systolic arraysmesh-connected arraysprogram compression

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20) Distributed algorithms (68W15)

Review text

Several techniques are described for compressing the size of programs on instruction systolic array in order to reduce bandwidth and storage requirements. Although the techniques have been designed for instruction systolic arrays they may also be applied successfully for other control structure like SIMD and MIMD.

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(6)

• Parallel merging on the instruction systolic array
• Boomerang Distinguisher for the SIMD-512 Compression Function
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• scientific article; zbMATH DE number 2086514 (Why is no real title available?)
• A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC
• A method of program compression based on the frequency characteristics of program behaviour

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