A novel sigma-delta modulator with fractional-order digital loop integrator
Summary: This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital \(P I^\lambda D^\mu\) controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.
- Performance evaluation of a third-order LADF sigma-delta \((\varSigma -\varDelta )\) modulator via FPGA implementation
- Robust \(H_{2}\) approach for digital correction of cascaded sigma delta modulators
- A design procedure for stable high order, high performance sigma-delta modulator loopfilters
- Design of a new fractional order \(\text{PI}^\lambda\)-\(\text{PD}^\mu\) controller based on SQP
- Stabilization of third-order, single-stage sigma-delta modulators
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