Accelerating lattice reduction with FPGAs

DOI10.1007/978-3-642-14712-8_8MaRDI QIDQ3584979zbMATH OpenOpenAlexFDO

Authors Jérémie Detrey, Guillaume Hanrot, Xavier Pujol, Damien Stehlé

Publication date 31 August 2010

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-14712-8_8

zbMATH Keywords

FPGAEuclidean latticesShortest Vector Problem

Mathematics Subject Classification ID

Symbolic computation and algebraic computation (68W30) Cryptography (94A60) Number-theoretic algorithms; complexity (11Y16)

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Cited in

(6)

• A Parallel Implementation of GaussSieve for the Shortest Vector Problem in Lattices
• Algorithms for the shortest and closest lattice vector problems
• Another 80-dimensional extremal lattice
• Hardware reduction for LUT-based Mealy FSMs
• Analysis of Gauss-sieve for solving the shortest vector problem in lattices
• I/O overhead and parallel VLSI architectures for lattice computations

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