Accelerating lattice reduction with FPGAs
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Publication:3584979
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Cited in
(6)- A Parallel Implementation of GaussSieve for the Shortest Vector Problem in Lattices
- Algorithms for the shortest and closest lattice vector problems
- Another 80-dimensional extremal lattice
- Hardware reduction for LUT-based Mealy FSMs
- Analysis of Gauss-sieve for solving the shortest vector problem in lattices
- I/O overhead and parallel VLSI architectures for lattice computations
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