Iddq testing-based diagnosis of faults in CMOS-circuits
From MaRDI portal
Publication:378377
zbMATH Open1274.94165MaRDI QIDQ378377FDOQ378377
Authors: Yu. V. Bykov, A. A. Ivanyuk, A. I. Yanushkevich, Vyacheslav Yarmolik
Publication date: 11 November 2013
Published in: Automation and Remote Control (Search for Journal in Brave)
Recommendations
- scientific article; zbMATH DE number 527269
- Testing cross-talk induced delay faults in digital circuit based on transient current analysis
- IDDQ testing technology for one-dimensional iterative logic arrays
- scientific article; zbMATH DE number 1106308
- I\(_{\text{DDT}}\): Fundamentals and test generation
Cited In (5)
- Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models
- IDDQ testing technology for one-dimensional iterative logic arrays
- Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells
- Infrastructure intellectual property for SoC simulation and diagnosis service
- Title not available (Why is that?)
This page was built for publication: Iddq testing-based diagnosis of faults in CMOS-circuits
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q378377)