Restructuring for fault-tolerant systolic arrays

DOI10.1109/12.16511zbMATH Open0666.68054OpenAlexW2083547484MaRDI QIDQ3817617FDOQ3817617

Authors: Hon F. Li, R. Jayakumar, Clement Lam 

Publication date: 1989

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.16511

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zbMATH Keywords

greedy algorithmfault tolerancerestructuringsystolic arraysdata skewingoptimal reconfiguraion

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80) Theory of software (68N99)

Cited In (11)

• On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors
• A systematic approach for designing concurrent error-detecting systolic arrays using redundancy
• On mapping algorithms to linear and fault-tolerant systolic arrays
• A built-in self-repair circuit for restructuring mesh-connected processor arrays by direct spare replacement
• On the complexity of testing for catastrophic faults
• Self-restructuring of mesh-connected processor arrays with spares assigned on rotated orthogonal side
• Degradable self-restructuring of processor arrays by direct spare replacement
• Title not available (Why is that?)
• Fault-tolerant schemes for some systolic systems
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• A fault-tolerant hexagonal systolic array

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