On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors

DOI10.1109/12.30846zbMATH Open0682.68009OpenAlexW2171196232MaRDI QIDQ4732082FDOQ4732082

Authors: Seyed H. Hosseini 

Publication date: 1989

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.30846

Recommendations

• Dynamically Restructurable Fault-Tolerant Processor Network Architectures
• Reconciling fault-tolerant distributed computing and systems-on-chip
• A study of two approaches for reconfiguring fault-tolerant systolic arrays
• scientific article; zbMATH DE number 4115981
• Restructuring for fault-tolerant systolic arrays
• scientific article; zbMATH DE number 4043772

zbMATH Keywords

fault detectionreconfigurationfault-tolerantarray processorserror recovery

Mathematics Subject Classification ID

Theory of software (68N99)

Cited In (9)

• An architecture for tolerating processor failures in shared-memory multiprocessors
• A fault-tolerant real-time multiprocessor with a built-in recovery mechanism
• A built-in self-repair circuit for restructuring mesh-connected processor arrays by direct spare replacement
• Testing and reconfiguration of VLSI linear arrays
• Fault tolerance in autonomous acoustic arrays
• Title not available (Why is that?)
• Run-Time Recovery Mechanism for Transient and Permanent Hardware Faults Based on Distributed, Self-Organized Dynamic Partially Reconfigurable Systems
• Title not available (Why is that?)
• Dynamically Restructurable Fault-Tolerant Processor Network Architectures

This page was built for publication: On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4732082)