Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method

MaRDI QIDQ5146162zbMATH OpenFDO

Authors

Publication date 25 January 2021

Full work available at URL http://mathnet.ru/eng/pdm70

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Recommendations

• Path delay fault test design for circuits obtained by covering ROBDDs with CLBs
• Synthesizing testable combinational circuits
• On the number of tests to detect all path delay faults in combinational logic circuits
• Synthesis of delay fault testability circuits
• A method for synthesis of easily-testable circuits in some basis admitting single fault detection tests of constant length

Cites work

• scientific article; zbMATH DE number 811541 (Why is no real title available?)
• Detection of Multiple Faults in Combinational Logic Networks

Cited in

(4)

• Gate-delay-fault testability properties of multiplexor-based networks
• Synthesis of delay fault testability circuits
• On the number of tests to detect all path delay faults in combinational logic circuits
• Path delay fault test design for circuits obtained by covering ROBDDs with CLBs

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