Reducing the number of LUTs for Mealy FSMS with state transformation
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Publication:6567112
DOI10.61822/AMCS-2024-0012MaRDI QIDQ6567112FDOQ6567112
Authors: Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek 
Publication date: 4 July 2024
Published in: International Journal of Applied Mathematics and Computer Science (Search for Journal in Brave)
Recommendations
- Improving the LUT count for mealy FSMS with transformation of output collections
- Improving characteristics of LUT-based mealy FSMs
- Hardware reduction for LUT-based Mealy FSMs
- Structural decomposition as a tool for the optimization of an FPGA-based implementation of a Mealy FSM
- Mixed encoding of collections of microoperations for a microprogram finite-state machine
Formal languages and automata (68Q45) Switching theory, applications of Boolean algebras to circuits and networks (94C11) Mathematical problems of computer architecture (68M07)
Cites Work
- Functional decomposition with application to FPGA synthesis
- Minimization of mealy finite-state machines by internal states gluing
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- Hardware reduction for LUT-based Mealy FSMs
- Improving characteristics of LUT-based mealy FSMs
- Embedded system design. Embedded systems foundations of cyber-physical systems, and the Internet of Things
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