Reducing the number of LUTs for Mealy FSMS with state transformation

DOI10.61822/AMCS-2024-0012MaRDI QIDQ6567112zbMATH OpenFDO

Authors Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek

Publication date 4 July 2024

Published in International Journal of Applied Mathematics and Computer Science (Search for Journal in Brave)

Copyright license Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported

Full work available at URL https://doi.org/10.61822/AMCS-2024-0012

zbMATH Keywords

combined state codesextended state codesFPGALUTMealy FSMsynthesis

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Formal languages and automata (68Q45) Switching theory, applications of Boolean algebras to circuits and networks (94C11)

Recommendations

• Improving the LUT count for mealy FSMS with transformation of output collections
• Improving characteristics of LUT-based mealy FSMs
• Hardware reduction for LUT-based Mealy FSMs
• Structural decomposition as a tool for the optimization of an FPGA-based implementation of a Mealy FSM
• Mixed encoding of collections of microoperations for a microprogram finite-state machine

Cites work

• Embedded system design. Embedded systems foundations of cyber-physical systems, and the Internet of Things
• Functional decomposition with application to FPGA synthesis
• Hardware reduction for LUT-based Mealy FSMs
• scientific article; zbMATH DE number 603377 (Why is no real title available?)
• scientific article; zbMATH DE number 1941087 (Why is no real title available?)
• scientific article; zbMATH DE number 2170622 (Why is no real title available?)
• Improving characteristics of LUT-based mealy FSMs
• Minimization of mealy finite-state machines by internal states gluing

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