Securing the AES finalists against power analysis attacks
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Cited in
(28)- Statistical properties of side-channel and fault injection attacks using coding theory
- Multivariate high-order attacks of shuffled tables recomputation
- On two DES implementations secure against differential power analysis in smart-cards
- Buying AES design resistance with speed and energy
- A first-order leak-free masking countermeasure
- On efficient leakage-resilient pseudorandom functions with hard-to-invert leakages
- Attacks and security proofs of EAX-prime
- Montgomery’s Trick and Fast Implementation of Masked AES
- Affine Masking against Higher-Order Side Channel Analysis
- A proposition to enhance a countermeasure scheme against power analysis attack for AES
- A New DPA Countermeasure Based on Permutation Tables
- Principles on the security of AES against first and second-order differential power analysis
- Private Circuits II: Keeping Secrets in Tamperable Circuits
- Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis
- Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
- AES side-channel countermeasure using random tower field constructions
- scientific article; zbMATH DE number 1950623 (Why is no real title available?)
- scientific article; zbMATH DE number 1979285 (Why is no real title available?)
- Bitslice ciphers and power analysis attacks
- scientific article; zbMATH DE number 1878339 (Why is no real title available?)
- Hamming weight attacks on cryptographic hardware -- breaking masking defense
- Маскирование ГОСТ 28147-89 для защиты от атак по побочным каналам
- A VLSI implementation of an SM4 algorithm resistant to power analysis
- Cryptographic Hardware and Embedded Systems - CHES 2004
- Advanced Encryption Standard – AES
- Cache Based Power Analysis Attacks on AES
- Applied Cryptography and Network Security
- Secure hardware implementation of nonlinear functions in the presence of glitches
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