Cited in
(36)- Brief Announcement: On Implementing Software Transactional Memory in the C++ Memory Model
- Empirical Bayesian smoothing splines for signals with correlated errors: methods and applications
- SMV: selective multi-versioning STM
- Speculative parallelization of sequential loops on multicores
- MiBench
- PARSEC
- STMBench7
- Autolocker
- Lee-TM
- Minebench
- SNZI
- SPLASH-2
- Specomp
- WormBench
- Feather-Trace
- ALPBench
- TPC-C
- DiSTM
- ebsc
- scsd
- SPEC Benchmarks
- AtomCaml
- AVIO
- NOrec
- PhTM
- JudoSTM
- RingSTM
- tm_db
- TMunit
- TLRW
- An analytic framework for performance modeling of software transactional memory
- Adaptive locks: combining transactions and locks for efficient concurrency
- Extensible transactional memory testbed
- Window-based greedy contention management for transactional memory: theory and practice
- Embedded-TM: energy and complexity-effective hardware transactional memory for embedded multicore systems
- A competitive analysis for balanced transactional memory workloads
This page was built for software: STAMP
