Systolic VLSI and FPGA Realization of Artificial Neural Networks

DOI10.1007/978-3-642-12775-5_15MaRDI QIDQ4929795zbMATH OpenOpenAlexFDO

Authors Pramod Kumar Meher

Publication date 24 September 2010

Published in Computational Intelligence in Optimization (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-12775-5_15

zbMATH Keywords

systolic arraysVLSI structures

Mathematics Subject Classification ID

Computer system organization (68M99) Learning and adaptive systems in artificial intelligence (68T05)

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