VLSI synthesis of DSP kernels. Algorithmic and architectural transformations

MaRDI QIDQ2743245zbMATH OpenFDO

Authors Mahesh Mehendale, Sunil D. Sherlekar

Publication date 27 September 2001

zbMATH Keywords

data flow graph transformationsdigital signal processing (DSP)distributed arithmeticDSP algorithmsDSP optimization kernelshardware/software multipliers and addersintegrated circuit technologyVLSI synthesisweighted sum computation

Mathematics Subject Classification ID

Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Biomedical imaging and signal processing (92C55) Software, source code, etc. for problems pertaining to information and communication theory (94-04) Communication theory (94A05) Signal theory (characterization, reconstruction, filtering, etc.) (94A12) Applications of design theory to circuits and networks (94C30)

Cited in

(5)

• Low power synthesis methodology with data format optimization applied on a DWT
• A framework for high level estimations of signal processing VLSI implementations
• A compact DSP core with static floating-point arithmetic
• Multidimensional DSP core synthesis for FPGA
• Design of data format converters using two-dimensional register allocation

This page was built for publication: VLSI synthesis of DSP kernels. Algorithmic and architectural transformations

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2743245)