Easily Testable Realizations ror Logic Functions

DOI10.1109/T-C.1972.223475zbMath0243.94032OpenAlexW2038539185MaRDI QIDQ5655292

Sudhakar M. Reddy

Publication date: 1972

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/t-c.1972.223475

Mathematics Subject Classification ID

Related Items (26)

Algorithms for conversion of minterms to positive polarity Reed-Muller coefficients and vice versa ⋮ Structure of modulo-2 ring-sum canonical expansions for boolean functions ⋮ Short single fault detection tests for logic networks under arbitrary faults of gates ⋮ A method for synthesis of easily-testable circuits in some basis admitting single fault detection tests of constant length ⋮ Families of Reed-Muller canonical forms ⋮ Invited paper. Boolean matrix representation for the conversion of minterms to Reed–Muller coefficients and the minimization of Exclusive-OR switching functions ⋮ Simplified theory of boolean functions ⋮ Short complete diagnostic tests for circuits with two additional inputs in some basis ⋮ Shannon function of the test length with respect to gate input identification ⋮ Power minimization of FPRM functions based on polarity conversion ⋮ On the exact value of the length of the minimal single diagnostic test for a particular class of circuits ⋮ Ring testing of discrete devices implementing polynomtal forms ⋮ Single fault detection tests for circuits of functional elements ⋮ SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES ⋮ Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates ⋮ Lower bounds for the lengths of single tests for Boolean circuits ⋮ A method of synthesis of irredundant circuits admitting single fault detection tests of constant length ⋮ Optimization of fixed-polarity Reed-Muller circuits using dual-polarity property ⋮ Multiple-level circuit solutions to the circuit non-decomposability problem of the set-theoretic modified reconstructability analysis (MRA) ⋮ Unit checking output tests under constant faults for functional elements ⋮ Check of linear combination circuits ⋮ New dimensions in non‐classical neural computing, part II: quantum, nano, and optical ⋮ Circuits form‐valued classical, reversible and quantum optical computing with application to regular logic design ⋮ New dimensions in non‐classical neural computing ⋮ On the relation between BDDs and FDDs ⋮ Short single tests for circuits with arbitrary stuck-at faults at outputs of gates

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