Short single fault detection tests for logic networks under arbitrary faults of gates
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Publication:5071224
DOI10.17223/20710410/55/4zbMath1490.94086OpenAlexW4285257033MaRDI QIDQ5071224
Publication date: 20 April 2022
Published in: Prikladnaya Diskretnaya Matematika (Search for Journal in Brave)
Full work available at URL: http://mathnet.ru/eng/pdm760
Switching theory, applications of Boolean algebras to circuits and networks (94C11) Boolean functions (94D10)
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- Single fault detection tests for circuits of functional elements
- Circuits admitting single-fault tests of length 1 under constant faults at outputs of elements
- Method of synthesis of easily testable circuits admitting single fault detection tests of constant length
- Short Complete Fault Detection Tests for Logic Networks with Fan-In Two
- ON LOGIC NETWORKS ALLOWING SHORT SINGLE FAULT DETECTION TESTS UNDER ARBITRARY FAULTS OF GATES
- SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES
- Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates
- A METHOD FOR CONSTRUCTING LOGIC NETWORKS ALLOWING SHORT SINGLE DIAGNOSTIC TESTS
- Easily Testable Realizations ror Logic Functions
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