On logic networks allowing short single fault detection tests under arbitrary faults of gates

DOI10.17223/20710410/51/4zbMATH Open1459.94174OpenAlexW3165696003MaRDI QIDQ4986237FDOQ4986237

Authors: Kirill A. Popkov 

Publication date: 27 April 2021

Published in: Prikladnaya Diskretnaya Matematika (Search for Journal in Brave)

Full work available at URL: http://mathnet.ru/eng/pdm732

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zbMATH Keywords

Boolean functionlogic networksingle fault detection test

Mathematics Subject Classification ID

Switching theory, applications of Boolean algebras to circuits and networks (94C11) Fault detection; testing in circuits and networks (94C12)

Cited In (20)

• Maximum ease of testability of logic circuits with respect to multiple stuck-on faults
• Complete fault detection tests of length 2 for logic networks under stuck-at faults of gates
• On self-correcting logic circuits of unreliable gates with at most two inputs
• Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates
• Testing by Verifying Walsh Coefficients
• Single diagnostic tests for inversion faults of gates in circuits over arbitrary bases
• Testable design of AND-EXOR logic networks with universal test sets
• Short single tests for circuits with arbitrary stuck-at faults at outputs of gates
• Short single fault detection tests for logic networks under arbitrary faults of gates
• SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES
• Shannon function of the test length with respect to gate input identification
• Detecting tests for Boolean functions in presence of local linear faults of the inputs of circuits
• MODIFIED TRANSITION MATRIX AND FAULT TESTING IN SEQUENTIAL LOGIC CIRCUITS UNDER RANDOM STIMULI WITH A SPECIFIED MEASURE OF CONFIDENCE
• Friedman's question: Detectability of bridging faults in irredundant computational logic networks
• Design of exclusive or sum-of-products (ESP) logic arrays with universal tests for detecting stuck-at and bridging faults
• Short Complete Fault Detection Tests for Logic Networks with Fan-In Two
• Simulation of faults in logical networks with races
• A method for constructing logic networks allowing short single diagnostic tests
• The length of single fault detection tests with respect to substitution of gates with inverters
• The length of single-fault detection tests with respect to substitution of inverters for combinational elements in some bases

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