Short single tests for circuits with arbitrary stuck-at faults at outputs of gates
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Publication:2332897
DOI10.1515/DMA-2019-0030zbMATH Open1490.94087OpenAlexW2982156900MaRDI QIDQ2332897FDOQ2332897
Publication date: 5 November 2019
Published in: Discrete Mathematics and Applications (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1515/dma-2019-0030
Recommendations
- Short single fault detection tests for logic networks under arbitrary faults of gates
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- Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates
- Single diagnostic tests for inversion faults of gates in circuits over arbitrary bases
- Maximum ease of testability of logic circuits with respect to multiple stuck-on faults
- Complete fault detection tests of length 2 for logic networks under stuck-at faults of gates
- SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES
- scientific article; zbMATH DE number 3922347
Switching theory, applications of Boolean algebras to circuits and networks (94C11) Fault detection; testing in circuits and networks (94C12) Boolean functions (94D10)
Cites Work
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- Synthesis of easily testable circuits over the Zhegalkin basis in the case of constant faults of type 0 at outputs of elements
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- SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES
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- LOWER BOUNDS FOR LENGTHS OF COMPLETE DIAGNOSTIC TESTS FOR CIRCUITS AND INPUTS OF CIRCUITS
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- Lower estimate of the length of the complete test in the basis \(\{x|y \}\)
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- Lower bounds for the lengths of single tests for Boolean circuits
- On unit diagnostic tests for constant faults of the same type at outputs of functional elements
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- On the exact value of the length of the minimal single diagnostic test for a particular class of circuits
Cited In (11)
- Maximum ease of testability of logic circuits with respect to multiple stuck-on faults
- Easily testable circuits in Zhegalkin basis in the case of constant faults of type ``1 at gate outputs
- On self-correcting logic circuits of unreliable gates with at most two inputs
- Title not available (Why is that?)
- On self-correcting logic circuits of unreliable gates
- Single diagnostic tests for inversion faults of gates in circuits over arbitrary bases
- Title not available (Why is that?)
- Efficient VLSI fault simulation
- Lower bound of the length of a single fault diagnostic test with respect to insertions of a mod-2 adder
- The length of single fault detection tests with respect to substitution of gates with inverters
- The length of single-fault detection tests with respect to substitution of inverters for combinational elements in some bases
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