Cryptographic Hardware and Embedded Systems - CHES 2004
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Cited in
(17)- Statistical properties of side-channel and fault injection attacks using coding theory
- Multivariate high-order attacks of shuffled tables recomputation
- Higher-order masking in practice: a vector implementation of masked AES for ARM NEON
- On the security of RSM -- presenting 5 first -- and second-order attacks
- Second-order power comparisons for a class of nonparametric likelihood-based tests
- A first-order leak-free masking countermeasure
- Boosting higher-order correlation attacks by dimensionality reduction
- Taylor expansion of maximum likelihood attacks for masked and shuffled implementations
- Formal analysis of the entropy / security trade-off in first-order masking countermeasures against side-channel attacks
- On Second-Order Differential Power Analysis
- Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
- Statistical Analysis of Second Order Differential Power Analysis
- Design of a Differential Power Analysis Resistant Masked AES S-Box
- Parallel Implementations of Masking Schemes and the Bounded Moment Leakage Model
- Higher-order masked Saber
- Secure hardware implementation of nonlinear functions in the presence of glitches
- Side-channel resistant crypto for less than 2,300 GE
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