Dynamically Restructurable Fault-Tolerant Processor Network Architectures

DOI10.1109/TC.1985.1676583MaRDI QIDQ3347791zbMATH OpenOpenAlexFDO

Authors Dhiraj K. Pradhan

Publication date 1985

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1985.1676583

zbMATH Keywords

binary treecircuit switchingdistributed systemdynamic processingfault- tolerant multiprocessor networksmodular networkpacket switchingparallel systemself-routing

Mathematics Subject Classification ID

Theory of operating systems (68N25) Theory of software (68N99) Applications of graph theory to circuits and networks (94C15)

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Cited in

(16)

• Chordal rings as fault-tolerant loops
• A depth-first search routing algorithm for star graphs and its performance evaluation
• IEH graphs. A novel generalization of hypercube graphs
• Incrementally extensible hypercube networks and their fault tolerance
• Balanced computation of two-dimensional transforms on a tree machine
• Run-Time Recovery Mechanism for Transient and Permanent Hardware Faults Based on Distributed, Self-Organized Dynamic Partially Reconfigurable Systems
• Task Migration for Fault-Tolerant FlexRay Networks
• A fault-tolerant mapping scheme for a configurable multiprocessor system
• Theg-network and its inherent fault tolerant properties
• Upper bounds on the connection probability for 2-D meshes and tori
• Efficient implementation techniques for gracefully degradable multiprocessor systems
• On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors
• scientific article; zbMATH DE number 2090487 (Why is no real title available?)
• A regular scalable fault tolerant interconnection network for distributed processing
• Enabling high reliability via matroidal connectivity and conditional matroidal connectivity on arrangement graph networks
• Nonplanar switchable arrays

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