On an Optimally Fault-Tolerant Multiprocessor Network Architecture

DOI10.1109/TC.1987.1676947MaRDI QIDQ4727426zbMATH OpenOpenAlexFDO

Authors

Publication date 1987

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1987.1676947

zbMATH Keywords

connectivityfault-tolerant networkmultiprocessor networkoptimal fault toleranceregular digraphsshuffle-exchange graph

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of software (68N99) Deterministic network models in operations research (90B10) Applications of graph theory to circuits and networks (94C15)

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