Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

DOI10.1109/TCSI.2010.2071830MaRDI QIDQ5010565zbMATH OpenOpenAlexFDO

Authors Xinmiao Zhang, Fang Cai

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tcsi.2010.2071830

Mathematics Subject Classification ID

Linear codes (general theory) (94B05) Decoding (94B35)

Cited in

(7)

• SCALABLE AND EFFICIENT IMPLEMENTATIONS OF THE LDPC DECODER USING RECONFIGURABLE MODELS
• scientific article; zbMATH DE number 6930419 (Why is no real title available?)
• An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation
• Fully Parallel Stochastic LDPC Decoders
• A Flexible NISC-Based LDPC Decoder
• A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
• Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture

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