Interleaved convolutional code and its Viterbi decoder architecture

DOI10.1155/S1110865703309126MaRDI QIDQ1773676zbMATH OpenFDO

Authors Jun Jin Kong, Keshab K. Parhi

Publication date 3 May 2005

Published in EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1155/S1110865703309126

zbMATH Keywords

burst-error correctioninterleaved convolutional codeinterleaved Viterbi decoderrandom-error correction

Mathematics Subject Classification ID

Convolutional codes (94B10) Burst-correcting codes (94B20) Decoding (94B35)

Review text

Summary: We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for the interleaved convolutional code. The state-parallel architecture uses as many add-compare-select (ACS) units as the number of trellis states. By replacing each delay (or storage) element in state metrics memory (or path metrics memory) and path memory (or survival memory) with \(I\) delays, an interleaved Viterbi decoder is obtained where \(I\) is the interleaving degree. The decoding speed of this decoder architecture is as fast as the operating clock speed. The latency of the proposed interleaved Viterbi decoder is `decoding depth (DD) \(\times\) interleaving degree \((I) + \text{extra delays }(A)\),' which increases linearly with the interleaving degree \(I\).

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Cited in

(2)

• An efficient in-place VLSI architecture for Viterbi algorithm
• Interleaver Design for Serially Concatenated Convolutional Codes: Theory and Application

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