Logic Test Pattern Generation Using Linear Codes

DOI10.1109/TC.1984.1676501MaRDI QIDQ3335684zbMATH OpenOpenAlexFDO

Authors Donald T. Tang, C. L. Chen

Publication date 1984

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1984.1676501

zbMATH Keywords

exhaustive test patternsintegrated circuitslinear feedback shift-registerslinear polynomial codesLogic testingtest pattern generationVLSI testing

Mathematics Subject Classification ID

Linear codes (general theory) (94B05)

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Cited in

(12)

• The use of linear sums in exhaustive testing
• Efficient VLSI fault simulation
• Analysis of a PRSA generator
• The pseudorandom sequence of arrays
• Recursive generation of locally complete tests
• Graph partitioning applied to the logic testing of combinational circuits
• Generating a PRSA with triangular symmetry
• Verification Testing—A Pseudoexhaustive Test Technique
• Exhaustive test pattern generation using cyclic codes
• \(t\)-CIS codes over \(\mathrm{GF}(p)\) and orthogonal arrays
• Computational Science and Its Applications – ICCSA 2004
• Formal Methods for Hardware Verification

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