Novel reversible fault tolerant error coding and detection circuits

DOI10.1142/S0219749911007447MaRDI QIDQ3015432zbMATH OpenFDO

Authors Majid Haghparast, Keivan Navi

Publication date 13 July 2011

Published in International Journal of Quantum Information (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1142/S0219749911007447

zbMATH Keywords

cyclic codefault toleranceHamming codelow power designnanotechnologyparity-preserving reversible circuitsquantum computationreversible logic design

Mathematics Subject Classification ID

Quantum computation (81P68) Quantum coding (general) (81P70) Statistical mechanics of nanostructures and nanoparticles (82D80) Cyclic codes (94B15)

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Cites work

• Conservative logic
• Fault-tolerant design
• scientific article; zbMATH DE number 5076264 (Why is no real title available?)
• Irreversibility and Heat Generation in the Computing Process
• Logical Reversibility of Computation
• Minimization and optimization of reversible bcd-full adder/subtractor using genetic algorithm and don't care concept

Cited in

(5)

• Designing parity preserving reversible circuits
• Novel qutrit circuit design for multiplexer, de-multiplexer, and decoder
• On design of parity preserving reversible adder circuits
• Optimization approaches for designing quantum reversible arithmetic logic unit
• Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

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