Performance analysis of asynchronous circuits using Markov chains

DOI10.1007/3-540-36190-1_9MaRDI QIDQ4417611zbMATH OpenFDO

Authors Peter A. Beerel, Aiguo Xie

Publication date 29 July 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2549/25490313.htm

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

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(9)

• Robust asynchronous implementation of Boolean functions on the basis of duality
• Testing asynchronous circuits: A survey
• Application of concurrency in the asynchronous design of write-after-read operations
• Performance Enhancement of Asynchronous Circuits
• Pre-synthesis Optimization for Asynchronous Circuits Using Compiler Techniques
• Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry
• Model checking the design of an unrestricted, stuck-at fault tolerant, asynchronous sequential circuit using SMV
• scientific article; zbMATH DE number 7566051 (Why is no real title available?)
• Communicating Sequential Processes. The First 25 Years

Describes a project that uses

Uses Software

• Petrify

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